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| Integrated Circuit Systems, Inc. ICS9250-11 Frequency Timing Generator for PENTIUM II/III Systems General Description The ICS9250-11 is a main clock synthesizer chip for Pentium II based systems using Rambus Interface DRAMs. This chip provides all the clocks required for such a system when used with a Direct Rambus Clock Generator (DRCG) chip such as the ICS9212-01, 02, 03 and a PCI buffer 9112-17. Spread Spectrum may be enabled by driving the SPREAD# pin active. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9250-11 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. The CPU/2 clocks are inputs to the DRCG. Features Generates the following system clocks: - 6 - CPU Clocks 100/133MHz (2.5V). - 2 - CPU/2 output for synchronous memory reference (2.5V). - 4 - fixed frequency Clocks @ 66.6MHz (3.3V). - 2 - fixed frequency Clocks @ 33.3MHz (3.3V). - 6 - IOAPIC Clocks @ 1/4 of CPUCLK or 16.667MHz, synchronous to CPU Clock (2.5V) - 1 - 48MHz Clock (3.3V) - 2 - REF Clocks @ 14.31818MHz 0.5% typical down spread modulation on CPU, PCI, IOAPIC, 3V66 and CPU/2 output clocks. Uses external 14.318MHz crystal. Block Diagram X1 X2 OSC 2 REF (0:1) Pin Configuration SPREAD# PLL Spread Spectrum 6 CPUCLK (0:5) /2 /3 C o n t r o l /3 /2 4 /4 /2 /2 6 IOAPIC(0:5) SEL 133/100# SEL(0:1) 2 CPU/2 (0:1) 3V66 (0:3) /2 2 3V33 (0:1) PLL2 48MHz Power Groups: VDDREF, GNDREF = REF, X1, X2 VDD66, GND66 = 3V66 VDD33, GND33 = 3V33 VDD48, GND48 = 48MHz VDDCOR, GNDCOR = PLL Core VDDLCPU, GNDLCPU = CPUCLK VDDLCPU/2 , GNDLCPU/2 = CPU/2 VDDLAPIC, GNDAPIC = IOAPIC 56-pin SSOP 9250-11 Rev C 3/20/00 Third party brands and names are the property of their respective owners. ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ICS9250-11 Pin Descriptions Pin number 1, 52, 53 Pin name GNDLAPIC Type PWR Description Ground pin for the IOAPIC outputs. 2.5V clock outputs running divide synchronous with the CPU (Host bus) clock frequency. The default APIC is running at 1/4 of CPUCLK frequency. When FREQ_APIC is strapped low, the APIC is running at fixed 16.67 MHz. If CPU = 133 MHz, APIC = CPU/8 If CPU = 100 MHz, APIC = CPU/6 Power pin for the IOAPIC outputs. 2.5V. Power pin for REF clocks XTAL_IN 14.318MHz crystal input XTAL_OUT Crystal output 3.3V 14.318 MHz clock output. APIC clock strapping option for fixed 16.67 MHz APIC clock outputs. If FREQ_APIC# = 0, APIC Clock = 16.67 MHz If FREQ_APIC# = Open, APIC Clock = CPU/4 3.3V 14.318MHz clock output. TEST# is sampled low (external with 10k pulldown). All clock outputs are Tri-State. power pin for the 3V66 clocks. 66MHz outputs at 3.3V. These outputs are stopped when CPU_STOP# is driven active.. Ground pin for 3V outputs. 3.3V Fixed 33MHz clock output. 3.3V power for PLL core. Ground pin for the 48MHz output Fixed 48MHz clock output. 3.3V Power pin for the 48MHz output. This selects the frequency for the CPU and CPU/2 outputs. High = 133MHz, Low=100MHz Function select pins. See truth table for details. Enables spread spectrum when active(Low). modulates all the CPU, PCI, IOAPIC, 3V66 and CPU/2 clocks. Does not affect the REF and 48MHz clocks. 0.5% down spread modulation. Power pin for the CPU/2 clocks. 2.5V 2.5V clock outputs at 1/2 CPU frequency. 66MHz or50MHz depending on the state of the SEL 133/100# input pin. Ground pin for the CPU/2 clocks. Ground pin for the CPUCLKs Host bus clock output at 2.5V. 133MHz or 100MHz depending on the state of the SEL 133/100MHz. Power pin for the CPUCLKs. 2.5V 2, 3, 50, 51, 54, 55 IOAPIC (0:5) OUT 4, 49, 56 5, 11 6 7 9 VDDLAPIC VDDREF X1 X2 REF0 FREQ_APIC# REF1 PWR PWR IN OUT OUT OUT OUT OUT PWR OUT PWR OUT PWR PWR OUT PWR IN IN IN PWR OUT PWR PWR OUT PWR 10 12, 19 13, 14, 17, 18 8, 15, 16, 23, 24 21, 22 25 26 27 28 29 30, 31 32 33 34, 35 TEST# VDD66 3V66[0:3] GND 3V33MHz VDDCOR GND48 48MHz VDD48 SEL 133/100# SEL[0:1] SPREAD# VDDLCPU/2 CPU/2[0:1] 36 GNDLCPU/2 37, 44, 45 GNDLCPU 38, 39, 42, 43, 46, CPUCLK[0:5] 47 40, 41, 48 VDDLCPU 2 ICS9250-11 Frequency Select: SEL SEL1 133/100# 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 SEL0 0 1 0 1 0 1 0 1 CPU MHz Tristate N/A 100 100 TCLK/2 N/A 133.3 133.3 CPU/2 MHz Tristate N/A 50.00 50.00 TCLK/4 N/A 66.6 66.6 3V66 MHz Tristate N/A 66.6 66.6 TCLK/4 N/A 66.6 66.6 3V33 48 REF MHz MHz MHz Tristate Tristate Tristate N/A N/A N/A 33.3 OFF 14.318 33.3 48 14.318 TCLK/8 TCLK/2 TCLK N/A NA N/A 33.3 OFF 14.318 33.3 48 14.318 IOAPIC MHz Tristate N/A CPUCLK/16.67 CPUCLK/16.67 TCLK/16 N/A CPUCLK/16.67 CPUCLK/16.67 1/4 1/4 1/4 1/4 Power Management Features: SEL 133/100# 0 0 0 0 1 1 1 1 SEL1 0 00 1 1 0 0 1 1 SEL0 0 1 0 1 0 1 0 1 Function All outputs Tri- State Reserved Active 100 MHz, 48 MHz PLL inactive Active 100 MHz, 48 MHz PLL active Test Mode Reserved Active 133 MHz, 48 MHz PLL inactive Active 133 MHz, 48 MHz PLL active 3 ICS9250-11 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . 0C to +70C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated) PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current SYMBOL VIH VIL IIH IIL1 IIL2 IDD3.3OP IDD.25OP Powerdown Current Input Frequency Pin Inductance 1 CONDITIONS MIN 2 VSS-0.3 -5 200 TYP VIN = VDD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors CL = Max loads; Select @ 100 MHz CL = Max loads; Select @ 133 MHz CL = Max loads; Select @ 100 MHz CL = Max loads; Select @ 133 MHz CL = Max loads Input address VDD or GND VDD = 3.3 V Logic Inputs Output pin capacitance X1 & X2 pins To 1st crossing of target frequency From VDD = 3.3 V to 1% target frequency Output enable delay (all outputs) Output disable delay (all outputs) CPU @ 1.25V, 3V66 @ 1.5V 3V66 @ 1.5V, 3V33 @ 1.5V CPU @ 1.25V, IOAPIC @ 1.25V MAX VDD+0.3 0.8 5 UNITS V V A A 160 160 75 90 200 100 14.318 7 5 6 22.5 3 1 1 0 1.5 1.0 3 8 8 1.5 3.5 3.0 mA mA A MHz nH pF pF pF ms ms ns ns ns ns ns Operating Supply Current IDD3.3PD IDD.25PD Fi Lpin CIN COUT CINX Ttrans TSTAB tPZH,tPZL tPHZ,tPLZ TCPU-3V66 T3V66-3V33 TCPU-IOAPIC Input Capacitance Transition time 1 1 1 13.5 18 Clk Stabilization Delay 1 Skew 1 1 Guaranteed by design, not 100% tested in production. 4 ICS9250-11 Electrical Characteristics - CPU TA = 0 - 70C; VDDL = 2.5 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time 1 SYMBOL VOH2B VOL2B IOH2B IOL2B tr2B tf2B dt2B CONDITIONS IOH = -12 mA IOL = 12 mA VOH @ MIN = 1.0 V VOH @ MAX = 2.375 V VOL @ MIN = 1.2 V VOL @ MAX = 0.3 V VOL = 0.4 V, VOH = 2.0 V VOH = 2.0 V, VOL = 0.4 V VT = 1.25 V VT = 1.25 V VT = 1.25 V MIN 2 -27 TYP MAX UNITS V 0.4 V -27 mA mA ns ns % ps ps 27 30 0.4 0.4 45 1.6 1.6 55 175 150 1 1 1 1 Duty Cycle Skew window 1 tsk2B tjcyc-cyc2B Jitter, cycle-to-cycle Guaranteed by design, not 100% tested in production. Electrical Characteristics - CPU/2 TA = 0 - 70C; VDDL = 2.5 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time 1 SYMBOL VOH2B VOL2B IOH2B IOL2B tr2B tf2B dt2B CONDITIONS IOH = -12 mA IOL = 12 mA VOH @ MIN = 1.0 V VOH @ MAX = 2.375 V VOL @ MIN = 1.2 V VOL @ MAX = 0.3 V VOL = 0.4 V, VOH = 2.0 V VOH = 2.0 V, VOL = 0.4 V VT = 1.25 V VT = 1.25 V VT = 1.25 V MIN 2 -27 TYP MAX UNITS V 0.4 V -27 mA mA ns ns % ps ps 27 30 0.4 0.4 45 1.6 1.6 55 175 250 1 1 1 1 Duty Cycle Skew window 1 tsk2B tjcyc-cyc2B Jitter, cycle-to-cycle Guaranteed by design, not 100% tested in production. 5 ICS9250-11 Electrical Characteristics - 3V33 TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time 1 SYMBOL VOH1 VOL1 IOH1 IOL1 tr1 tf1 dt1 CONDITIONS IOH = -14.5 mA IOL = 9.4 mA VOH @ MIN = 1.0 V VOH @ MAX = 3.135 V VOL @ MIN = 1.95 V VOL @ MAX = 0.4 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V MIN 2.4 -33 TYP MAX UNITS V 0.4 V -33 mA mA ns ns % ps ps 30 38 0.5 0.5 45 2.0 2.0 55 250 250 1 1 1 1 Duty Cycle Skew window 1 tsk1 tjcyc-cyc1 Jitter, cycle-to-cycle Guaranteed by design, not 100% tested in production. Electrical Characteristics - 3V66 TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time 1 SYMBOL VOH1 VOL1 IOH1 IOL1 tr1 tf1 dt1 CONDITIONS IOH = -14.5 mA IOL =9 mA VOH @ MIN = 1.0 V VOH @ MAX = 3.135 V VOL @ MIN = 1.95 V VOL @ MAX = 0.4 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V MIN 2.4 -33 TYP MAX UNITS V 0.4 V -33 mA mA ns ns % ps ps 30 38 0.5 0.5 45 2.0 2.0 55 250 500 1 1 1 1 Duty Cycle Skew window 1 tsk1 tjcyc-cyc1 Jitter, cycle-to-cycle Guaranteed by design, not 100% tested in production. 6 ICS9250-11 Electrical Characteristics - REF, 48MHz TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time 1 SYMBOL VOH5 VOL5 IOH5 IOL5 tr5 tf5 dt5 CONDITIONS IOH = -16 mA IOL = 9 mA VOH @ MIN = 1.0 V VOH @ MAX = 3.135 V VOL @ MIN = 1.95 V VOL @ MAX = 0.4 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V, Fixed clocks VT = 1.5 V, Ref clocks MIN 2.4 -29 TYP MAX UNITS V 0.4 V -23 mA mA ns ns % ps ps 29 27 1.0 1.0 45 4.0 4.0 55 500 1000 1 1 1 1 Duty Cycle Jitter, cycle-to-cycle Jitter, cycle-to-cycle 1 tjcyc-cyc5 tjcyc-cyc5 Guaranteed by design, not 100% tested in production. Electrical Characteristics - IOAPIC TA = 0 - 70C; VDDL = 2.5 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time 1 SYMBOL VOH2B VOL2B IOH2B IOL2B tr2B tf2B dt2B CONDITIONS IOH = -12 mA IOL = 12 mA VOH @ MIN = 1.0 V VOH @ MAX = 2.375 V VOL @ MIN = 1.2 V VOL @ MAX = 0.3 V VOL = 0.4 V, VOH = 2.0 V VOH = 2.0 V, VOL = 0.4 V VT = 1.25 V VT = 1.25 V VT = 1.25 V MIN 2 -27 TYP MAX UNITS V 0.4 V -27 mA mA ns ns % ps ps 27 30 0.4 0.4 45 1.6 1.6 55 250 250 1 1 1 1 Duty Cycle Skew window 1 tsk2B tjcyc-cyc2B Jitter, cycle-to-cycle Guaranteed by design, not 100% tested in production. 7 ICS9250-11 Pin 1 D/2 .093 DIA. PIN (Optional) Index Area E/2 PARTING LINE H L DETAIL "A" TOP VIEW BOTTOM VIEW -eA2 c B A .004 C SEE DETAIL "A" -E-DEND VIEW A1 SEATING PLANE -C- SIDE VIEW SYMBOL A A1 A2 B c D E e H h L N COMMON DIMENSIONS MIN. NOM. MAX. .095 .102 .110 .008 .012 .016 .087 .090 .094 .008 .0135 .005 .010 See Variations .291 .295 .299 0.025 BSC .395 .420 .010 .013 .016 .020 .040 See Variations 0 8 VARIATIONS AD MIN. .720 D NOM. .725 N MAX. .730 56 "For current dimensional specifications, see JEDEC 95." Dimensions in inches 56 Pin 300 mil SSOP Package Ordering Information Example: ICS9250yF-11-T Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP ICS XXXX y F - PPP - T Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device 8 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. |
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